Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip
Jafari, F., Jantsch, Axel and Lu, Zhonghai 2016. Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24 (12), pp. 3387-3400.
|Authors||Jafari, F., Jantsch, Axel and Lu, Zhonghai|
We propose an approach for computing the end-to-end delay bound of individual variable bit-rate flows in an First Input First Output multiplexer with aggregate scheduling under weighted round robin (WRR) policy. To this end, we use a network calculus to derive per-flow end-to-end equivalent service curves employed for computing least upper delay bounds (LUDBs) of the individual flows. Since the real-time applications are going to meet guaranteed services with lower delay bounds, we optimize the weights in WRR policy to minimize the LUDBs while satisfying the performance constraints. We formulate two constrained delay optimization problems, namely, minimize-delay and multiobjective optimization. Multiobjective optimization has both the total delay bounds and their variance as the minimization objectives. The proposed optimizations are solved using a genetic algorithm. A video object plane decoder case study exhibits a 15.4% reduction of the total worst case delays and a 40.3% reduction on the variance of delays when compared with round robin policy. The optimization algorithm has low run-time complexity, enabling quick exploration of the large design spaces. We conclude that an appropriate weight allocation can be a valuable instrument for the delay optimization in on-chip network designs.
|Keywords||network-on-chip (NoC); performance evaluation; Network calculus; worst case delay optimization; weight configuration|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Journal citation||24 (12), pp. 3387-3400|
|Accepted author manuscript|
|Digital Object Identifier (DOI)||doi:10.1109/TVLSI.2016.2556007|
|24 May 2016|
|Publication process dates|
|Deposited||08 Mar 2017|
|Copyright information||© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.|
|Book title||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
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